Hariharan M S
Hardware Intern - INTEL | MTech @ NIT CALICUT ’2026 | Ex-DV Engineer ACL Digital
- Role
- Hardware Intern at Intel
- Location
- Erode, TN, IN
- LinkedIn followers
- 500 followers
About Hariharan M S
Around 3.5 years of experience in IP and SS level verification- Proficient in developing testbench environments and conducting verification using SystemVerilog (SV) and Universal Verification Methodology (UVM)- Experienced in register verification, testbench development such as agent, monitor and scoreboard and the analysis of coverage reports, including both code and functional coverage- Hands-on experience with AMBA VIPs, such as APB, AXI, CHI, and Low Power Interface (LPI) protocols- Languages known: C, C++, Python, Perl, make file, Verilog, SystemVerilog, UVM- Expertise with tools such as Synopsys Verdi and Cadence Jasper Gold.
Experience
Hardware Intern
May 2025 — Present · Bengaluru, IN
Education
National Institute of Technology Calicut
MTech in Elctronics and Communication Engineering Department
2024 — 2026
Builders Engineering College
Bachelor of Engineering - BE
2016 — 2020
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