Hari Prasanth Govindaraju
Design Verification Engineer at Microsoft
- Role
- Senior Dv at Microsoft
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
About Hari Prasanth Govindaraju
Design Verification Engineer @ Microsoft and Masters Student from University of Southern California interested in ASIC Design Verification/ Logic Design / Embedded Software Development.Work Experience - Senior Engineer @ Qualcomm Atheros & Marvell Semiconductor, ASIC Design Engineer @ Sandisk Corporation, IP Design Intern @ Intel Corporation-Technical Skill set:Hardware Description Languages: Verilog, System Verilog, and VHDLVerification Methodologies: UVMScripting: PERLSimulators: Modelsim, QuestaSim, Cadence Virtuoso (Spectre)Synthesis: Xilinx ISE (FPGA), Nexys3 (FPGA), ADEPT(GUI)Logic Analyzers: Chipscope Pro (ILA & ICON)Static Timing Analyzers: Prime TimeLanguages : C/C++, PERL
Experience
Senior Dv
Jul 2024 — Present · Mountain View, CA, US
Education
University of Southern California
Master of Science (M.S.), Electrical Engineering (Digital VLSI & Comp Architecture)
Coimbatore Institute of Technology
Bachelor of Engineering (BE), Electrical and Electronics Engineering
2006 — 2010
Skills
- Cadence Virtuoso
- Matlab
- Asic
- Clearcase
- Embedded C
- System Verilog
- Chipscope Pro
- Verilog
- Xilinx Ise
- Ascet
- Modelsim
- Perl
- Embedded Systems
- C++
- Questasim
- C
- Systemverilog
- Vhdl
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