Hari Krishna Balupala

About Hari Krishna Balupala

VLSI Design Engineer with 7 years of experience in 7nm, 16nm and 65nm FPGA Chip/Block Design Verification and error control coding.Skills• Low Power Design (writing UPF’s for Power management using Power switches, Level Shifter, Isolation and Retention strategies).• Low Power Verification (Static verification using CLP and Dynamic Verification using VCS).• Delivered Xilinx Homogeneous and Heterogeneous designs in system-level integration.• Ultra RAM RTL Design, Verification (Smoke test, Compilation, Lint).• Pattern Generation and Validation of Memory on Silicon.• Formal Verification (LEC - RTL vs RTL, RTL vs Netlist, Netlist vs Netlist at Chip/Block level).• Behavioural RTL Verification (RTL vs Spice Netlist).• FPGA ARM ROM’s functional Verification using ESP.• BSDL generation • Error control codes designs like Hamming codes, BCH codes.Career highlights• Emerging star award in March 2022.• Boost award and Spark award for excellence in 2021, 2020.• Delivered Versal, Ultrascale+ family series chips for 2 consecutive years in 2020-22.

Experience

1. Senior Silicon Design Engineer

   AMD

   Feb 2022 — Present · Hyderabad, IN

   Deliver RTL checks and ROM’s for all FPGA tapeouts.• Low power design and Verification: Ultra RAM Blocks for next generation FPGA products.• Conformal ECO on various integration Modules

Education

• Sri Chaitanya College of Education

  Intermediate , MPC in Vijayawada, Andhra Pradesh

• Indian Institute Of Information Technology Allahabad

  Bachelor of Technology - BTech, Electronics and Communication Engineering in IIIT Allahabad

  2014 — 2018