Hargovind Sahu
SoC | RTL Design and Architecture | Synthesizable Transactor IP | Design for the Verification | AMBA | Cache Coherency | Infra SoC | PCIe | CXL| CHI | AXI | AHB | CSI | I2C | I2S
- Role
- Principal Engineer at Arm
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hargovind Sahu
Having experience in RTL design and architecture, synthesizable Verification IP, and Digital IP.Experience with coherency protocols (AMBA-CHI) and other on-chip communication protocols like AXI, AXI4stream, AHB, APB (Created various transactors for protocol.Expertise Verilog HDL design, System Verilog, C++/C, UVM, and System-Verilog based Test environment development using OPPS concept.
Experience
Principal Engineer
Dec 2022 — Present · Bengaluru, IN
Education
Saraswti Higher secondery school Narsinghpur
12th, Scince
1993 — 2002
Shri G S Institute of Technology & Science
BE, Electronics & Instrumentatin
2003 — 2007
Skills
- Algorithms
- Physical Design
- Very-Large-Scale Integration (Vlsi)
- Processors
- Fpga
- Asic
- C
- Verilog
- Rtl Design
- I2c
- Integrated Circuit Design
- Static Timing Analysis
- C++
- Xilinx
- Systemverilog
- Modelsim
- Debugging
- Perl
- Embedded Systems
- Eda
- Shell Scripting
- Usb
- Soc
- Functional Verification
- Open Verification Methodology
- System on a Chip (Soc)
- Arm
- Ncsim
- Specman
- Vhdl
- Vlsi
- Application-Specific Integrated Circuits (Asic)
- Perl Script
- Tcl
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