Hareesh G
Physical Design Engineer
- Role
- Physical Design Engineer at Appex Semiconductor Pvt Ltd
- Location
- Warangal, TG, IN
- LinkedIn followers
- 500 followers
About Hareesh G
Good Knowledge on all aspects of physical design including Synthesis, Floorplanning, Power Planning, Placement, Clock tree Synthesis, Parasitic Extraction, Timing Closure, Power/IR Drop(Static & Dynamic)Hands on Experience on implementation of block level designs in cutting edge process technologies like 45nm,22nm & below.Hands on Experience on Implementation of Top level designs Good Knowledge of EDA Tools from cadence (GENUS, TEMPUS, INNOVAS)Have a good knowledge on Languages like Verilog, HDL.Hands on Experience on scripting languages like Tcl, Perl.
Experience
Physical Design Engineer
Aug 2024 — Present · Bengaluru, IN
Education
JNTUH College of Engineering Hyderabad
Master of Technology - MTech, VLSI System Design
2015 — 2017
JNTUH College of Engineering Hyderabad
Bachelor of Technology - BTech, Electronics and Communications Engineering
2010 — 2014
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