Hareesh Babu P.
senior soc verification engineer
- Role
- Senior Soc Verification Engineer at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Hareesh Babu P.
Expertise in Soc/IP/Subsystem pre silicon verification:1. expertise in validation of design for debug Ip\'s both at soc and ip level.2.expertise in closed chassis debug validation over USB/I2C on Arm/IA based architecture. Raw and packet based debug tracing.3.expertise in amba protocols.4.expertise in IP and subsystem validation of Ethernet 10G MAC and PCS layer.5.Implemented VIP/BFM for 10G Mac and PCS.6.strong knowledge on Design for debug architecture and Ethernet 1G/10G/100G MAC/PCS layer architecture and protocol.7.Expertise on low power validation.8.Expertise in system verilog, UVM,OVM, SVA, random constrained and coverage models.9.expertise in post silicon debug support.
Experience
Senior Soc Verification Engineer
Apr 2022 — Present · OR, US
Education
Vikashighschool
SSC, ssc
Jntuk
Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering
2010 — 2014
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