Hardik Vaghela
ASIC Digital Design Engineer Sr. Staff at Synopsys Inc
- Role
- Sr Staff Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Hardik Vaghela
Experienced ASIC-Digital design engineer
Experience
Sr Staff Engineer
Jan 2025 — Present · Bengaluru, IN
Education
Indian Institute of Technology, Bombay
MTech - Master of Technology, CTARA
2012 — 2013
NIT Jalandhar
Master of Technology (M.Tech.), VLSI-Design
2013 — 2015
Skills
- Verilog
- Very-Large-Scale Integration (Vlsi)
- System Verilog
- Semiconductor Device
- Rtl Design
- Digital Ic Design
- Application-Specific Integrated Circuits (Asic)
- Vlsi Cad
- Uvm
- Digital Circuit Design
- Vlsi
- Systemverilog
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