Hardik Agrawal
Physical Design Engineer at Google | IIT Kharagpur
- Role
- Silicon Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Hardik Agrawal
An accomplished Physical Design Engineer with close to 6 years of experience delivering high-performance silicon from RTL2GDS across 7+ tapeouts on advanced technology nodes. Proven expertise in leading end-to-end physical implementation for complex, high-frequency designs and subsystems with a focus on optimizing PPA by bridging the gap between RTL design and Physical Implementation.
Experience
Silicon Engineer
Jul 2020 — Present · Bengaluru, IN
Leading RTL2GDS physical design efforts for an in-house LPDDR6/5x/5 memory controller IP/subsystem, from synthesis and floorplanning through PnR to final signoff and tapeout
Education
Indian Institute of Technology, Kharagpur
B.Tech. (Hons.), Electronics and Electrical Communication Engeneering
2015 — 2020
Indian Institute of Technology, Kharagpur
M.Tech., Microelectronics & VLSI Design
2015 — 2020
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