Hao Zhang

About Hao Zhang

Worked as a hardware engineer in ASIC design verification field with responsibility of verifying, debugging on block/subsystem level RTL, utilizing FPGA platform on prototyping and emulation, bring-up and testing on SOC level ASICs for Self-Driving System. Looking for a hardware (ASIC/FPGA) related position where to utilize the skills and experience and expand knowledge in related areas.SKILLS-Programming Languages: SystemVerilog, Verilog, C/C++, TCL, Python-Methodology: UVM, OOP, Block level and Top level verification of ASIC-Tool: Synopsys’s VCS, Verdi, Xilinx SDK, Xilinx Vivado, file version control process (SVN, P4V, Clearcase), Makefiles/CMake, IXIA IxExplorer and IxAutomate. email: h••••••••@gmail.com

Experience

1. Staff Design Engineer

   Black Sesame Technologies Inc

   Jul 2019 — Present · San Jose, CA, US

   RTL Design, Emulation/FPGA validation, Chip bring-up

Education

• Syracuse University

  Master of Science (M.S.), Computer Engineering

  2009 — 2011

Skills

• Asic
• Tcl
• Computer Architecture
• C
• Uvm (Universal Verification Methodology)
• Systemverilog
• Cadence Virtuoso
• Modelsim
• C++
• Synopsys Vcs, Dve and Verdi
• Verilog
• Computer Hardware
• Matlab