Haoyang Zhang
DV Engineer @Apple | DV Intern @ Sunlune | MS EE 25’ @University of Southern California
- Role
- Design Verification Engineer at Apple
- Location
- Sunnyvale, CA, US
- LinkedIn followers
- 500 followers
About Haoyang Zhang
Hi! I\'m Haoyang Zhang, a Hardware Enthusiast in :Digital Design \\ CPU Design \\ SoC DesignDigital VerificationComputer ArchitectureDesign For Testing Education:University of Southern California, Electrical Engineering, Master\'s Degree, CAXidian University, Electrical Engineering, Bachelor\'s Degree, ChinaSkills:Coding languages: SystemVerilog, VHDL, Verilog, C++Protocols: AMBA(AHB, APB,AXI), PCIe, UARTTools: UVM, Vivado, Modelsim, Cadence VirtuosoEmployers \\ Classmates \\ Anyone who loves Hardware, Feel free to reach out to me here on LinkedIn!
Experience
Design Verification Engineer
Jun 2025 — Present · Cupertino, CA, US
Education
Beijing No.2 Middle School
High School
University of Southern California
Master of Science - MS, Electrical Engineering
Xidian University
Bachelor's degree, Electrical and Electronics Engineering
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