Haonan Liu

ASIC Engineer @NVIDIA

Role
Asic Design Efficiency Engineer at NVIDIA
Location
Santa Clara, CA, US
LinkedIn followers
500 followers

About Haonan Liu

ASIC Engineer at NVIDIA. Former Hardware Engineer intern at Qualcomm. MS @UCLA. BS @Zhejiang University.

Experience

  1. Asic Design Efficiency Engineer

    NVIDIA

    Jan 2024 — Present · Santa Clara, CA, US

    RTL Performance/Perf verification of NVIDIA GPU’s computing core: Streaming Multiprocessor

Education

  • Zhejiang University

    Bachelor of Engineering - BE

    2018 — 2022

  • UCLA

    Master of Science - MS

    2022 — 2023

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Haonan Liu — Asic Design Efficiency Engineer at NVIDIA in Santa Clara, CA, US | Unifers