Haonan Liu
ASIC Engineer @NVIDIA
- Role
- Asic Design Efficiency Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Haonan Liu
ASIC Engineer at NVIDIA. Former Hardware Engineer intern at Qualcomm. MS @UCLA. BS @Zhejiang University.
Experience
Asic Design Efficiency Engineer
Jan 2024 — Present · Santa Clara, CA, US
RTL Performance/Perf verification of NVIDIA GPU’s computing core: Streaming Multiprocessor
Education
Zhejiang University
Bachelor of Engineering - BE
2018 — 2022
UCLA
Master of Science - MS
2022 — 2023
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