Sai Kp
ASIC Design Verification Engineer
- Role
- Soc Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Sai Kp
A result oriented professional with 16+ years of experience in verification- Good understanding of PCIE Protocol, Hands on experience with multiple VIP from vendors - Denali, Avery etc- Good understanding of NVMe- Good understanding of UCIe- Good understanding of CXL - Hands-on experience in verification environment development, identifying and writing test cases, achieving coverage goals, Gate level Simulations, verification strategies and methodologies- Experience in post silicon lab testing and software interaction.
Experience
Soc Design Engineer
Feb 2021 — Present · Bengaluru, IN
Verification of 2 Generations of SmartNIC / IPU at SoC and IP level.NVME, PCIe, CXL
Education
VEDANT , SEMICONDUCTOR COMPLEX LTD., MOHALI
Advanced PG Diploma in VLSI, VLSI
2006 — 2006
Jawaharlal Nehru Technological University
Bachelor of Engineering (B.E.), Electronics and Communications Engineering
2003 — 2006
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.