Hang Li
Senior ASIC Engineer, Nvidia
- Role
- Senior Hardware Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Hang Li
Excellent VLSI/Computer Architecture/OS/Algorithm and SW/HW acceleration Knowledge -Nvidia Streaming Multiprocessor-Data Analytics Accelerator ASIC (DAX), Speedup SQL Analytic Database/Algorithm/parallel computing by magnitude (HW/SW co-design from Scratch, Verilog)-Heterogenous multi core with fast context switching (big.LITTLE Architecture)-MIPS R10K Out of Order 2-way Superscalar Processor (Start from Scratch Verilog)-Fully customize Schematic Layout 16bit RISC processor with low power eDRAM(Start from Scratch for every single transistor except ISA decoder)
Experience
Senior Hardware Engineer
Nov 2017 — Present · San Francisco, CA, US
Pushing the GPU Streaming Multi-processors efficiency to the Speed of light
Education
Nanning No.2 High School, China
Highschool
2005 — 2008
University of Electronic Science and Technology of China
Bachelor's Degree, ECE
2008 — 2012
University of Michigan
Master's Degree, Computer Engineering
2012 — 2014
Stanford University
Graduate Non-degree
2020 — 2020
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