Haneet Rana
Assistant Registrar @Sardar Patel University
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WORK HISTORY
Assistant Registrar @Sardar Patel University
Mandi, IN
EDUCATION
National Institute of Technology Hamirpur Alumni
Master of Technology, Signal Processing Control Engineering
ABOUT HANEET RANA
Having exposure in DFT Domain, SCAN Insertion, fixing DRC violations, Test Compression insertion, OCCinsertion, JTAG, ATPG (Pattern Generation for Stuck-at, At-speed and IDDQ Test), Fault Coverage improvement, Fault Grading, Gate level simulation with Zero delay, with timing and debugging the same.Exposure on Synopsys Tool: DFT Compiler, DFTMax, BSD (Boundary Scan Design) compiler, Tertamax, DVE, VCS tools. Electronic Design Package: Silvaco TCAD TOOL, Cadence Virtuoso, Xilinx ISE, MATLAB & Simulink.Basic shell scripting skills.
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