Haidarabbas Nurbhanej
Vlsi Physical Verification Engineer @Wipro
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WORK HISTORY
Vlsi Physical Verification Engineer @Wipro
Bengaluru, IN
EDUCATION
ASIC Physical Design Engineer trainee
RV-VLSI VLSI and Embedded Systems Design Center
St.Xavier's School Himmatnagar
Schooling
Gujarat Technological University, Ahmedabad
Bachelor in ELECTRONICS & COMMUNICATION
ABOUT HAIDARABBAS NURBHANEJ
Design Rule Check (DRC). Layout Versus Schematic (LVS). Implementing Timing Closure ECOs using Synopsys IC Complier II which includes Cell insertion, Net Improvement Congested routing Vt Swap and Cell Sizing. Density violations, Antenna Effect, Latch up issue, Cross Talk, EM/IR fixes, ERC fixes. Hands on experience in Floorplan | Power plan | Placement | Clock tree synthesis | Routing | Static timing analysis | TCL | Custom routes EDA Tools: Synopsys PrimeTime, Synopsys IC compiler ll, Calibre, Innovus, ICV
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