Hafsal Moochikkal

About Hafsal Moochikkal

Experienced Senior Engineer with a demonstrated history of working in the VLSI industry. Skilled in Physical Design, Timing Closure, Physical verification, STA, TCL, Python and Integrated Circuits (IC). Strong engineering professional with a Master of Technology (M.Tech.) focused in VLSI from ER & DCI IT.

Experience

1. Senior Staff Engineer

   Qualcomm

   May 2022 — Present · Bangalore, IN

   Synthesis Implementation Lead for the Video/EVA subsystem across premium to low-tier mobile, XR, Auto, and compute chips. Delivered high-quality netlists on advanced Samsung and TSMC nodes-> Led PPA optimization and low-power design implementation-> Performed synthesis, pre-layout STA, CLP and formal verification-> Created a dashboard interface for hierarchical synthesis, STA, and CLP-> Built Python utilities for paranoia checks, IO delay validation, and clock frequency comparison-> Ensured high-quality IO constraints and contributed to flow enhancements for synthesis and verification.

Education

• ER & DCI IT

  Master of Technology (M.Tech.), VLSI

  2006 — 2008

• TKM College of Engineering

  Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering

  2002 — 2006

Skills

• Logic Synthesis
• Application-Specific Integrated Circuits (Asic)
• Soc
• Physical Design
• Vlsi
• Rtl Coding
• Fpga
• Asic
• Perl
• Embedded Systems
• Timing Closure
• Very-Large-Scale Integration (Vlsi)
• C
• Python
• Rtl Design
• System on a Chip (Soc)
• Static Timing Analysis
• Field-Programmable Gate Arrays (Fpga)
• Tcl
• Vhdl
• Formal Verification