Gyanendra Ayer
Field Process Engineer (Na Intel Dfs Process Etch) @Lam Research
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WORK HISTORY
Field Process Engineer (Na Intel Dfs Process Etch) @Lam Research
Hillsboro, OR, US
Semiconductor R&D engineer working on dry etch process development supporting Intel for next generation technologies Collaborated with multi-disciplinary teams of process, integration, and product engineers to define process and device performance targets and understand device and tool failure mechanisms Developed baseline recipe in Lam Kiyo tool and work with multiple teams for process transfer into production at customer site (Intel) Studied surface modifications/treatments using selective etch tools, such as Selis/Prevos/Argos, designed to help accelerate chipmakers’ 3D logic and memory roadmaps Analyzed data for internal alignment and customer meeting and update scorecard on a regular basis
EDUCATION
University of South Carolina
Doctor of Philosophy - PhD, Chemistry and Materials science
Tribhuvan University
Master of Science - MS, Physical Chemistry
ABOUT GYANENDRA AYER
Semiconductor R&D dry etch process engineer, working independently as well as…
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