Gyan Prakash Kashyap

WORK HISTORY

EDUCATION

ABOUT GYAN PRAKASH KASHYAP

10+ Years of Experience in ASIC Physical Design implementation (from Netlist to GDS) Techniques along with Expertise in multiple backend domains/tools. Exposure on Multiple Tapeouts across different technology nodes on complex, congested, timing critical & low power/multi voltage designs (SOCs/IPs & 3DIC SOCs). • Proficient & Expertise in Floorplanning, Powerplan, Place and Route, Clock Tree Synthesis, Routing, STA, Timing Closure, ECOs Implementation & Physical Verification. • Strong working experience on all the Techniques to resolve the Congestion/Timing/VCLP/PV/IR issues in the blocks having multiple number of macros, multi million gate counts, multiple power domains & frequencies up to 3GHZ. • Good exposure on TOP level full chip PNR, having multiple Blocks & Macros. Worked on Top Level IO Planning, IO PAD placement, IO tapping, Custom Signal routings & Automation of Custom PG mesh and PG ring Creation & Custom Clock routing. • Worked on TSMC (7nm), Samsung (2nm, 3nm, 4nm, 5nm, 7nm, 8nm, 10nm, 14nm, 18nm & 130nm), & Intel (14nm) Technology nodes. • Proficient & Expertise in Physical Verification, DRC/Density/ERC/Softcheck/DFM/LVS clean up, antenna fixes & Timing/Functional ECO\'s Implementation. • Excellent debugging skills to root cause the issues in the design/flow. Find solution through work around scripts till we get the tool fixes. • Strong Scripting knowledge in TCL to automate the PNR work flow & automating the various design challenges using Scripts, according to the requirement. • Excellent interpersonal skills with abilities to meet deadline & work under pressure. • Technically Proficient with proven ability to handle multiple blocks with critical issues and deliver the project on-time with quality. • Tools used (FC, ICC2, Calibre, StarRC, Primetime, VCLP, Formality & Spyglass)