Gus Espinosa
Intel Fellow, Chief Technologist in Dependable Computing @Intel
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WORK HISTORY
Intel Fellow, Chief Technologist in Dependable Computing @Intel
Portland, OR, US
EDUCATION
Cornell University
BS, Electrical Engineering
Boston University
MS, Computer Engineering
Cornell University
Bachelor of Electrical Engineering
Boston University
Master of Computer Engineering
SKILLS
ABOUT GUS ESPINOSA
I have a strong and proven track record of leading teams in the development of microprocessors for the high-volume PC and server market segments. My experience spans the design, architecture development, and validation of custom VLSI CPUs. I have worked on many of Intel’s major microprocessor designs since the 486 generation and served as the chief architect of several Intel® Pentium® Intel® Pentium® 4, and Intel® Xeon Phi™ microprocessors. In my current role, I am responsible for driving the development of architectural solutions for Intel\'s discrete GPUs to meet our product reliability/availability/serviceability (RAS) and security for dependable computing objectives. In more recent roles, I led functional safety architecture development for Intel\'s silicon platforms, where I was responsible for developing technology to establish industry-leading functional safety capability across Intel\'s product portfolio. Prior to that, I led the soft IP enabling program within the Intel Custom Foundry. I drove the development of Intel Architecture processor soft IP (BaseIA) and led the technology enablement effort to implement it on Intel\'s 14nm technology. This processor IP was featured in Spreadtrum\'s SC9861G-IA smartphone SOC, manufactured by Intel Custom Foundry.In the area of high-performance computing, I was the lead architect for the Larrabee processor, a high-end many-core chip aimed at 3D graphics and other throughput-oriented computing applications, and I led the architecture development team for Intel\'s Knights processor family. This new line of microprocessors, branded as the Intel® Xeon Phi™ line, was optimized for highly parallel, high performance computing applications. The first product based on this architecture, code-named Knights Corner, was announced at the International Supercomputer Conference \'12. This processor powered the #1 supercomputer in the world, the Tianhe-2 (Milky Way-2) system, from the June 2013 to June 2016 editions of the Top 500 list Specialties: My areas of interest and technical expertise include computer and systems architecture, processor microarchitecture and microcode design, computer systems performance analysis, reliability, dependable computing, and security.
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