Gururaju B. Puttaraju
DDR/LPDDR PHY IP Architecture and Design at Synopsys Inc | Computer Architecture and RTL Design | USC MSc. Electrical Engineering
- Role
- R & d Engineering, Senior Engineer at Synopsys Inc
- Location
- Austin, TX, US
- LinkedIn followers
- 500 followers
About Gururaju B. Puttaraju
I am a ASIC Design Engineer/Junior Architect with hands-on experience spanning CPU and GPU high-level architecture and microarchitecture, and high-speed memory subsystem design, with a strong focus on building clean, scalable, silicon-proven RTL. My work reflects a systems mindset where architectural intent, power efficiency, and long-term product robustness are treated as first-order constraints.At Synopsys, I contribute to the Architecture and customization of DDRx/LPDDRx PHYs for advanced SoCs, including DDR5, MRDIMM, and early LPDDR6 designs. I am part of Architecture team that works closely with RTL design, Verification, and physical design teams to translate evolving standards and customer requirements into configurable PHY solutions that meet aggressive timing and power targets while remaining reusable across product generations.Previously, at Maxim Integrated (Analog Devices), I gained early exposure to mixed-signal systems, strengthening my intuition for silicon behavior and reinforcing a disciplined approach to design correctness and integration.I hold a Master’s degree in Electrical Engineering (Computer Arch and Digital VLSI) from the University of Southern California (USC), where I implemented a fully functional Out-of-Order (OoO) CPU engine in SystemVerilog, including components like reorder buffers, issue logic, execution pipelines, and precise exception handling. I also designed key GPU architecture components, developing a solid understanding of parallel execution models and throughput-oriented hardware structures.I am motivated by building high-quality silicon through thoughtful architecture, rigorous RTL, and close cross-functional collaboration.
Experience
R & d Engineering, Senior Engineer
Jan 2024 — Present · Austin, TX, US
Architecting and designing next generation DDR and LPDDR PHY IPs.
Education
University of Southern California
Master of Science - MS, Electrical Engineering (Computer Architecture and VLSI)
B. M. S. College of Engineering
Bachelor of Engineering - BE, Electronics and Communications Engineering
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