Guruprasad Sardeshpande

ASIC DV Engineer at Meta | AI Silicon | Ex-Intel Xeon Server SoC Division

Role
Asic Dv Engineer at Meta
Location
Bengaluru, KA, IN
LinkedIn followers
500 followers
Information TechnologyView LinkedIn profile

About Guruprasad Sardeshpande

Total 10+ years of experience in the areas of SoC and Subsystem Verification mainly in SV based UVM/OVM environments- I seek a technically challenging position & responsibilities in building subsystem/SoC level verification environment, define validation scope, development of constrained random test-suite to verify the correctness of the design & achieve functional coverage closure.Verification Specialties Developed the small blocks of the VIP Good understanding of SystemVerilog, UVM Test Bench Architecture Developed SV – UVM TB Components with directed, random & constrained random approach Expertise in building testcases for given specification Created Virtual sequencer to handle APB Master & SPI Slave agent traffic Code & Functional Coverage Analysis Protocol Knowledge : PCIe, CXL, Coherency flows, AMBA AXI, AHB SKILL HDL’s : VerilogHVL’s : SystemVerilogVerification Methodology : UVM, OVMEDA Tools : Synopsys VCS-DVE, Cadence NCsim, Mentor Graphics QuestaSim Operating systems : Linux, Windows

Experience

  1. Asic Dv Engineer

    Meta

    May 2026 — Present · Bengaluru, IN

Education

  • Visvesvaraya Technological University

    Bachelor of Engineering (B.E.), Electronics and Communications Engineering

    2010 — 2013

  • S.G Balekundri Institute of Technology

    Bachelor of Engineering (BE), Electronics & Communication.

    2010 — 2013

Skills

  • Rtl Design
  • Microcontrollers
  • 8051 Microcontroller
  • Vhdl
  • Top-Down & Bottom-Up Design Methodologies
  • Verilog
  • Electronics
  • Assembly Language
  • Xilinx
  • Systemverilog
  • Making Projects on Fpga & Microcontroller
  • Embedded C
  • Moore & Mealy Machines
  • Matlab
  • Arm
  • Ovm
  • Xilinx Ise
  • Unix Operating Systems
  • Pcb Design
  • Usb
  • C
  • Multisim
  • Vlsi
  • Vhdl & Verilog Hdl Coding
  • Logic Design
  • Uart
  • Analog & Digital Communication Systems
  • Rtl Coding
  • Fpga
  • Asic
  • Uvm
  • Digital Signal Processors
  • Analog Circuit Design
  • Spi
  • I2c
  • System Design
  • Integrated Circuit Design
  • Microprocessors
  • Clock Tree Synthesis
  • Circuit Design

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Guruprasad Sardeshpande — Asic Dv Engineer at Meta in Bengaluru, KA, IN | Unifers