Gurinder Pal Singh
Layout Engineer at Texas Instruments
- Role
- Layout Engineer at Texas Instruments
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
Experience
Layout Engineer
Oct 2017 — Present · Bengaluru, IN
Leading the full chip layout execution. Developing floor plan that achieves best utilization of Silicon area. Generating layout schedule and provide area estimation details to Design lead. Handling Packing & Assembly checks.Deriving blocks analog layout(full chip) constraints from design requirements. Area efficient & parasitic aware block & IC layout. Working with expert teams to get the IC layout approved for ESD/LU/EM-IR. Running checkers on layout & take design to PG. Supporting PG process through review
Education
ARMY SCHOOL BATHINDA CANTT
10
1998 — 2003
Guru Gobind Singh College of Engg: & Tech
Bachelor's Degree
2006 — 2009
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