Gunavant Chaudhari
Senior Circuit Design Engineer at Xilinx
- Role
- Senior Circuit Design Engineer at Xilinx
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Gunavant Chaudhari
PLL Circuit DesignSerdes designLab characterizationSi Debugging
Experience
Senior Circuit Design Engineer
Aug 2015 — Present · San Jose, CA, US
PLL Design and validation.
Education
Portland State University
Master’s Degree, Analog-Mixed Signal Engineering
2008 — 2010
VIT, Pune
Bachelor’s Degree, Electrical and Electronics Engineering
Skills
- Semiconductors
- Integrated Circuit Design
- Analog
- Rtl Design
- Asic
- Pll
- Testing
- Simulations
- Systemverilog
- Cmos
- Analog Circuit Design
- Mixed Signal
- Circuit Design
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