Gunashekhar Prakash

About Gunashekhar Prakash

With over six years of experience as a Design for Test (DFT) Engineer, I have honed my skills in the intricate art of ensuring the reliability and quality of semiconductor devices. My expertise lies in the strategic implementation of DFT methodologies, including TAP, IJTAG, Boundary Scan, MBIST, SSN, and Tessent Flows, specifically focused on RTL insertion and validation. Throughout my career, I have been instrumental in integrating test features directly into RTL designs, optimizing them for seamless validation and robust fault coverage. My proficiency in TAP and IJTAG has enabled the efficient insertion of test access points, while my experience with Boundary Scan has ensured comprehensive testing of digital interfaces. I excel in deploying MBIST techniques to verify memory integrity and applying SSN strategies to mitigate signal integrity issues. Leveraging Tessent Flows, I have automated and enhanced the test generation and validation processes, ensuring that designs meet stringent quality standards. My ability to work collaboratively with design and verification teams has been key to successfully validating complex systems and driving project milestones. I am passionate about staying ahead of industry trends and continuously expanding my knowledge to tackle emerging challenges in DFT. My commitment to innovation and excellence drives me to contribute to the development of cutting-edge technologies that shape the future of semiconductor testing. Let\'s connect to explore opportunities for collaboration and innovation in the dynamic field of DFT!

Experience

1. Sr Silicon Design Engineer (Dft)

   AMD

   Aug 2025 — Present · Bengaluru, IN

Education

• RV VLSI

  Post-graduation Diploma, VLSI Front End

  2018 — 2019

• RN Shetty Institute of Technology

  Bachelor of Engineering - BE, Electronics and Communications Engineering

  2014 — 2018

• BITS Pilani Work Integrated Learning Programmes

  Master of Technology - MTech, Microelectronics