Gulab Sayyad

About Gulab Sayyad

Currently a Physical Design Engineer at Microsoft, contributing to the netlist to GDSII flow of ASIC designs. Responsibilities include floorplanning, placement, clock tree synthesis (CTS) debug, routing, and physical verification. Skilled in PNR and signoff closure processes, with experience in advanced technology nodes such as 2nm to 28nm. Lead Physical Design Engineer with 8 years of hands-on experience in high-performance ASIC design, excelling at leading complex design projects from concept to tape-out. •Executed physical design implementation for subchip, ensuring alignment with project specifications•Mentored five junior engineers while maintaining full ownership and accountability for the subchip-level design and delivery.•Led timing closure for a highly critical subchip with dense interface-communication by data and clock paths maintaining proactive and clear communication with all subchip owners to align timing closure during Tap-out•Validated clock tree architecture during CTS to meet skew and latency constraints•Wrote timing ECOs and Tcl scripts to resolve DRVs, including max transition, max capacitance, signal integrity, and setup/​hold violations, ensuring robust timing closure and signoff quality.•Proactively analyzed timing violations, provided feedback to constraint owners, and developed local constraints to resolve timing violation and reduce TNS•Proficient in timing and SDC constraint generation and management; strong debugging skills•Resolved static, signal EM and dynamic IR drop issues, ensuring power integrity met peak conditions.•Worked on Low Power Design and Having deep knowledge on UPF & Low Power Cells.•Executed synthesis, place & route, and timing closure for multimillion-gate SoC designs.•Utilized major EDA tools including Synopsys, and Mentor Graphics for process optimization.•Applied expertise in FinFET technologies at 16nm, 14nm, and below for advanced designs.•Designed power grids complying with EMIR specifications to enhance performance.•Generated and implemented ECOs to resolve timing noise and EMIR violations effectively.•Proficient in TCL, Perl, scripting for automation and analysis tasks.•Generated ETM NDM, LEF, UPF, DEF and SPEF.Holds a degree in Electronics and Communications Engineering from Rajiv Gandhi University of Knowledge Technologies, Nuzvid. Demonstrates proficiency in physical verification, placement customizations, and CTS debug, leveraging experience from prior roles at HCL Technologies, LeadSoc Technologies, Xilinx, and Samsung Electronics to deliver high-quality designs.

Experience

1. Physical Design Engineer

   Microsoft

   Sep 2023 — Present · Hyderabad, IN

   Executed physical design implementation for subchip, ensuring alignment with project specifications•Mentored five junior engineers while maintaining full ownership and accountability for the subchip-level design and delivery.•Led timing closure for a highly critical subchip with dense interface-communication by data and clock paths maintaining proactive and clear communication with all subchip owners to align timing closure during Tap-out•Validated clock tree architecture during CTS to meet skew and latency constraints•Wrote timing ECOs and Tcl scripts to resolve DRVs, including max transition, max capacitance, signal integrity, and setup/​hold violations, ensuring robust timing closure and signoff quality.•Proactively analyzed timing violations, provided feedback to constraint owners, and developed local constraints to resolve timing violation.•Proficient in timing and SDC constraint generation and management; strong debugging skills•Resolved static, signal EM and dynamic IR drop issues, ensuring power integrity met peak conditions.•Worked on Low Power Design and Having deep knowledge on UPF & Low Power Cells.•Executed synthesis, place & route, and timing closure for multimillion-gate SoC designs.•Utilized major EDA tools including Synopsys, and Mentor Graphics for process optimization.•Applied expertise in FinFET technologies at 16nm, 14nm, and below for advanced designs.•Designed power grids complying with EMIR specifications to enhance performance.•Generated and implemented ECOs to resolve timing noise and EMIR violations effectively.•Proficient in TCL, Perl, scripting for automation and analysis tasks.•Resolved timing violations by analyzing data and clock paths, subsequently implementing ECOs through clock path tuning.•Generated ETM NDM, LEF, UPF, DEF and SPEF.•Received appreciation from DRI and Project Manager for exceptional contributions in resolving critical timing violations through targeted ECOS, directly supporting timing closure.

Education

• IIIT Nuzvid

  Bachelor of Technology, Electrical, Electronics and Communications Engineering

• RAJIV GANDHI UNIVERSITY OF KNOWLEDGE TECHNOLOGIES, NUZVID

  IIIT Nuzvid, Electronics and Communications Engineering

  2014 — 2018

• IIIT Innovation In IT

  Bachelor of Technology, Electrical, Electronics and Communications Engineering