Guan Wang
- Role
- Senior Asic Design Engineer at NVIDIA
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Guan Wang
Cache coherent interconnect architect; CHI protocol/coherency expert Different…
Experience
Senior Asic Design Engineer
Feb 2018 — Present
CPU interconnect and protocol handling; Designed and implemented protocol bridging unit; Experience about BW & latency in different CPU network; arch/uarch experience in CPU interconnect Worked on ARM IP integration and Error Handling logic;
Skills
- Xilinx Ise
- Asic
- Vlsi
- Cadence
- Rtl Design
- Cadence Virtuoso
- Signal Processing
- C
- Machine Learning
- Fpga
- Perl
- Logic Design
- Matlab
- Xilinx
- Systemverilog
- Vhdl
- Control Systems Design
- Verilog
- Digital Electronics
- Proteus
- Computer Architecture
- Integrated Circuit Design
- Circuit Design
- Modelsim
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