Greg Steiert
- Role
- Altera
- Location
- Seattle, WA, US
- LinkedIn followers
- 500 followers
Experience
Present
Education
Caltech
BS, Electrical Engineering
1992 — 1996
Skills
- Pcb Design
- Verilog
- Debugging
- System Architecture
- Field-Programmable Gate Arrays (Fpga)
- Fpga
- Asic
- Product Development
- Perl
- Embedded Systems
- Electrical Engineering
- Application-Specific Integrated Circuits (Asic)
- Rtl Design
- Processors
- Microcontrollers
- Microprocessors
- Hardware
- Circuit Design
- Firmware
- Semiconductors
- Vhdl
- Analog
- Hardware Architecture
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