Gande Sai Vineeth

About Gande Sai Vineeth

Experienced Analog & Mixed signal IC Layout design engineer Hands on experience in Fin-FET & Planar technologies which includes TSMC (2nm, 5nm, 7nm, 12nm, 16nm & 28nm), Intel 3nm. In depth familiarity in layout design for sub blocks of SERDES Phy i.e, RX, TX, PLL Expertise in physical verification (DRC, LVS), Electrical Checks (ERC), DFM checks (PM, Missing vias, Density checks) Knowledge of layout effects i.e, Matching, Reliability, Antenna, Proximity effects, Spacing effects, Stress effects. Aware of layout techniques to mitigate ESD, latch-up & overcoming max density and min density challenges. Knowledge of design for reliability i.e, EM, IR Knowledge of signal integrity issues i.e, clock/data routes, differential routing, shielding Exposure to industry standard EDA tools like Cadence Virtuoso & Synopsys Custom Compiler for Schematic and Layout Edit. Calibre & ICV for Layout Verification like DRC, LVS, and StarRC for PEX (Parasitic) Extraction

Experience

1. Senior Engineer, Hbm Layout

   Micron Technology

   Jul 2025 — Present · Hyderabad, IN

   Cadence Virtuoso)• Worked on TSMC 12nm (HBM 4)Worked on 8-channel sub blocks.• Presently working on TSMC 3nm (HBM 5)Working on TSV to PHY routings. Optimising by using methodology flows.

Education

• Narayana Junior College, Tarnaka

  Intermediate, MPC

• CVR College of Engineering, Hyderabad

  Bachelor of Technology - BTech, Electrical, Electronics and Communications Engineering

  2014 — 2018

• VNR Vignana Jyothi Institute of Engineering and Technology (VNRVJIET)

  Master of Technology - MTech, VLSI System Design