Grigor H.

About Grigor H.

Experience in- Synthesis to GDSII flows with Synopsys and Cadence tools- Low Power Physical Design Flows- Most state of art technologies - Project Management- Cross-functional team communication* Full understanding of digital circuit Front End and Back End design flows (Synthesis, DFT, Floorplaning, physical synthesis, placement, clock tree synthesis, routing, extraction, STA, formal verification, physical verification, timing closure).* Logic Design, RTL design Verilog HDL, VHDL (basic knowledge), writing test bench, RTL and gate level simulation and debugging* Experience in Xilinx /Altera FPGA design flows - IES design suite (for logic design and DSP), Experience in ISE CORE Generator. Basic knowledge in Xilinx devices’ (Slices, Configurable Logic Blocks (CLBs), Input Output Blocks (IOBs), DSP elements, memories etc.)- Quartus II software, MegaCore IP wizard. Basic knowledge in Altera devices’ (Logic Array Blocks (LAB), Adaptive Logic Module (ALM), Look-up tables (LUT), DSP elements, memories etc.)- Experience in Synopsys FPGA tool Synplify Pro/Primer* Analog design, PLL, transimpedance amplifiers for optical receivers.* Familiar with Basics of HTML.* Scripting TCL, and Perl, KSH, SED, CSH, BASH.Can be good team player, individual contributor and take leadership role.

Experience

1. Senior Principal Physical Design Engineer

   Tenstorrent

   May 2024 — Present · Santa Clara County, CA, US

   AI chiplet – Top‑level ownership- Own top‑level floorplanning and pushdown for a next‑generation AI chiplet, defining subsystem shapes, placement strategy, and pinouts across a replicated tile array with extensive multi‑instantiation, mirroring, and rotation- Lead full‑chip bump / RDL alignment to maintain consistent clock, NoC, D2D, and power connectivity between tiles, chiplet top, and package.SMU – RTL‑to‑GDSII technical lead- PD lead for SMU from RTL to GDSII, driving SDC/UPF strategy and sign‑off across STA, PV, EMIR, LEQ, and VCLP, and shaping padring architecture, bump map, and padring/RDL/bump generation- Lead cross‑functional closure with RTL, DFT, PD, packaging, and foundry teams to resolve timing, power‑integrity, and interface‑constraint issues and achieve SMU sign‑off.Other chiplets – Early architecture & floorplanning-Support early architectural floorplanning for two additional chiplets, exploring partitioning and mixed‑signal IP placement, and providing top‑level floorplan guidance for detailed implementation.

Education

• State Engineering University of Armenia

  Masters, IC technology and design (VLSI design)

  2005 — 2007

• UC Berkeley Extension

  Certificate, Project Management

  2014 — 2017