Ben Gribstad
DFT Lead at Google
- Role
- Dft Lead at Google
- Location
- Mountain View, CA, US
- LinkedIn followers
- 500 followers
About Ben Gribstad
20+ years of VLSI design experience ranging from full custom high speed transistor level design to automated RTL-to-GDSII ASIC flows using external and internal IP, more recently focusing on hierarchical DFT and ATPG. I have expertise in digital back-end design and flow development, including full chip synthesis, place and route, DFT logic definition, design and implementation for ATPG and MBIST, DFT insertion and verification. I am a strong believer in design re-use and automation. I\'m interested in ASIC and semi-custom flow development, methodology definition, and exciting challenges in hardware design.Specialties: Semi-custom and ASIC backend flow development and implementation, Design for Test, ATPG, MBIST, LBIST, JTAG, (iJTAG). Cross-functional and cross-cultural communication and leadership.
Experience
Dft Lead
May 2020 — Present
Education
University of Minnesota
BSEE, Electrical Engineering, Computer Science Minor
University of California, Berkeley
MSEE, Digital and Analog Circuit Design
Skills
- Rtl Design
- Cmos
- Dft
- Project Management
- Perl
- Soc
- Jtag
- Cross-Functional Team Leadership
- Vlsi
- Distributed Team Management
- Asic
- Verilog
- Low-Power Design
- Atpg
- Physical Design
- Rtl Simulation
- Hardware Architecture
- Clock Tree Synthesis
- Mixed Signal
- Circuit Design
- Ic
- Semiconductors
- Logic Synthesis
- Timing Closure
- Logic Design
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