Greg Burda

About Greg Burda

Highly-motivated, results-driven technical leader of teams developing high-speed, low-power memories and foundational IPs across a broad range of compute and artificial intelligence products. 20+ years of experience with a track record of productive collaboration across a variety of teams, including architecture, physical design, CAD/EDA, DFT, process technology, post-silicon, and product engineering teams. From concept to productization, my team\'s charter is to provide differentiated memory and DTCO standard cell IP and solutions that give Microsoft products a strategic advantage in the marketplace.

Experience

1. Director of Engineering

   Microsoft

   Jul 2018 — Present · Raleigh-Durham, NC, US

   Director of circuit and CAD/EDA team designing memory and foundational IPs for a broad range of compute and AI products. Custom memories, DTCO stdcell, clocking circuits, storage elements, structured datapath, testchip design on multiple process nodes with full RTL-to-GDS responsibilities and more. CAD/EDA teams develop methodologies for simulation, LPE, physical verification, timing, functional verification, infrastructure, etc. Created scalable architecture for advanced process node testchips and led teams performing RTL, DV, PD, circuit, board & package, and post-silicon characterization.

Education

• Wilkes University

  BSEE, Electrical Engineering

  1994 — 1998

Skills

• Eda
• Asic
• Integrated Circuit Design
• Microprocessors
• Circuit Design
• Processors
• Verilog
• Simulations
• Testing