Gowrishankar N J

About Gowrishankar N J

Staff R&D Engineer | EDA Industry | Timing Constraints & STA SpecialistExperienced Research & Development Engineer with a strong background in Electronic Design Automation (EDA), currently contributing as a Staff R&D Engineer at Synopsys. I specialize in developing advanced timing constraints management features within the ASIC design flow, driving innovation in sign-off tools and prototyping/emulation platforms. Core Expertise:Object-Oriented System Design, Design Patterns, Algorithms, and Data StructuresStatic Timing Analysis (STA), Timing Constraints Analysis, and BudgetingPerformance & Capacity Optimization of Software SystemsParallel Computing, Multi-threading, and Dynamic ProgrammingGeneric C++ Library Development for EDA ToolsCross-Product Feature Integration and Scalable Software Architectures Technical Skills:Programming Languages: C, C++, Tcl, Python, BashTools: Perforce (SCM), GDB (Debugging), Sun Studio Profiler (Performance Analysis) Professional Highlights:Developed robust methodologies and solutions to manage complex timing constraints in state‑of‑the‑art, multi‑billion‑instance SoC designs for top-tier chip makers.Architected and managed constraint analysis features for high-performance EDA toolsLed optimization of in-memory databases and graph-based algorithms for timing analysis.Delivered customer-centric solutions for complex timing and design challenges.Built robust software frameworks for FPGA prototyping and emulation platforms.Passionate about solving complex engineering problems through elegant software design and high-performance computing. Always eager to collaborate, innovate, and push the boundaries of what\'s possible in chip design automation.

Experience

1. Staff Engineer, Research and Development Engineer

   Synopsys Inc

   Apr 2024 — Present · Sunnyvale, CA, US

   Design & Development of Synopsys Timing constraints management software tools

Education

• SJM Polytechnic

  Diploma Of Engineering

  2009 — 2012

• B. M. S. College of Engineering

  Bachelor of Engineering - BE

  2012 — 2015

• Birla Institute of Technology and Science, Pilani

  Master of Technology - MTech

  2017 — 2019

Skills

• Microsoft Excel
• C
• Microsoft Office
• Matlab
• Arm
• C++
• Testing
• Digital Signal Processors
• Knowledge of Linux
• Perforce
• Verilog
• Fpga
• Vhdl
• Embedded C
• Field-Programmable Gate Arrays (Fpga)
• Very-Large-Scale Integration (Vlsi)
• Microcontrollers
• Linux
• Computer Architecture
• Tcl
• Application-Specific Integrated Circuits (Asic)
• Electronics
• Gnu Debugger
• Shell Scripting
• Semiconductors
• Perl
• Embedded Systems