Govind Soni
Lead Design Engineer at Cadence Design Systems
- Role
- Lead Design Engineer at 铿腾设计系统公司
- Location
- Durg, CG, IN
- LinkedIn followers
- 500 followers
About Govind Soni
I am currently working as an Analog Design Engineer at the Cadence SSG DDRIO team. My Design experience includes both Custom Digital blocks like FIFO path for Deserialisation and analog Blocks like Duty Cycle Monitor and DAC for Data and Clock Paths in high speed transmission architecture in all Intel22, Tsmc 3nm, Tsmc 5nm, Intel18A and Tsmc 2nm.I have also worked on the Positive charge pump system as part of my college project and Negative Charge pump architecture during my internship at Micron Technology.As a part of my Master\'s Thesis Program, I have worked on Low power SRAM Cache and also I have done project on complete Asic Design flow.My area of interest includes Analog CMOS design,Mix Signal Circuits Design,Digital VLSI Design, Memory Circuit Design and Asic flow.
Experience
Lead Design Engineer
Jan 2026 — Present · Bengaluru, IN
Education
Bhilai Institute of Technology (BIT), Durg
Bachelor of Engineering - BE, Electrical and Electronics Engineering
2013 — 2017
Indraprastha Institute of Information Technology, Delhi
Master of Technology - MTech, VLSI and Embedded System
2019 — 2021
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