Govind Maurya

About Govind Maurya

RTL Design (R&D) Engineer in FPGA department with 5+ years of experience in PCIe Gen5 and Gen6 subsystem development and validation. Deep expertise in PCIe PHY layer, including LTSSM, TX/RX PCS, speed change flows, and high-speed datapath processing. Strong proficiency in VHDL and Verilog, with end-to-end FPGA design and hardware bring-up on Xilinx Virtex platforms. Extensive hands-on experience with PCIe VIPs, interoperability testing with multiple DUTs like AMD, Intel etc. Currently working as a Module Lead, guiding R&D teams and delivering robust, standards-compliant PCIe solutions and parellaly debugging complex rtl issues.

Experience

1. Module Lead

   Logic Fruit Technologies

   Apr 2023 — Present · Gurugram, IN

   Keysight Loki/Vision – PCIe Gen6 1) Built deep expertise in PCIe PHY behavior, including LTSSM transitions, speed changes, loopback, and high-speed datapath processing.2) Modified previously existing RTL modules of PCIe Gen6 LTSSM,TX/RX PCS, compliant with protocol and linktraining requirements.3) Executed full FPGA design flow on Xilinx Virtex platforms, from synthesis through timing closure and bitstream generation.4) Verified functionality of Design using Avery PCIe BFM IP and back-to-back simulations in QuestaSim ensuring 100% protocol compliance.5) Validated and debugged PCIe links using BER analysis (Keysight M8070B), Vivado ILA, Mark Debug, and simulation-to-silicon correlation.@ERNIC 1) Analyzed and documented FPGA design blocks, detailing interconnections, functional behavior, and end-to-end data flow to support design understanding and onboarding.2) Tuned ERNIC IP configuration parameters to achieve targeted throughput and performance objectives on FPGA platforms.@CREDO 1) Successfully debugged numerous tests for Credo Semiconductors with Avery BFM environment connected back to back with single and double retimers connected in between while using Avery PHY interface.2) Built custom test cases to verify loopback and compliance functionalities of the Retimer DUT.3) Gave multiple PCIe protocol demonstrations to the client about topics such as gen6 linkup, data rate change, LTSSM overview, etc.

Education

• Motilal Nehru National Institute Of Technology

  Bachelor of Technology - B.Tech, ECE

  2016 — 2020