Gourav Singhal

About Gourav Singhal

RTL to GDSII full Asic flow,Synthesis, Floorplanning,PnR, CTS, Timing Closure, power analysis, IR drop analysis, DRC and LVS clean up, chip Sign off, Full-custom, deep sub-micron design and layout of Cache memory.Specialties: Synthesis, Floorplanning,PnR, CTS, Timing Closure, power analysis, IR drop analysis, DRC and LVS clean up, chip Sign offprogramming in perl, SRAM memory designing

Experience

1. Engineering Manager

   Cisco

   Nov 2020 — Present · Bangalore, IN

Education

• Dr. A.P.J. Abdul Kalam Technical University

  B.tech, Electronics and Commmunication

  2003 — 2007

• Manipal Institute of Technology

  MS in Microelectronic, Microelectronic

  2009 — 2011

• Sandeepani School of VLSI Design, Bangalore

  PG Diploma, Advance PG Diploma in VLSI Design

  2007 — 2008

Skills

• Soc
• Logic Design
• Rtl to Gds Full Flow
• Low Power Design
• Timing Closure
• Signal Integrity
• Drc
• Asic
• Perl
• Route
• Semiconductors
• Integrated Circuit Design
• Microprocessors
• Circuit Design
• Power Analysis
• Vlsi
• Verilog
• Physical Verification
• Sram
• Timing
• Physical Design
• Digital Design
• Static Timing Analysis
• Digital Electronics
• Xilinx
• Cmos
• Primetime
• Floorplanning
• Lvs
• Ic
• Tcl