Gopikrishnan Viswanadhan

About Gopikrishnan Viswanadhan

Most of my professional experience is with Processor/ASIC/SoC/IP Verification.I am currently involved in verifying processor chips; especially the system bus and IO unit.I have been involved in development of IP core verification methodologies, environments using SystemVerilog, OVM and UVM.I also do a bit of formal verification of control structures; I love writing assertions using PSL -).I have working experience with PCI Express bus protocol verification.I developed verification environments for memory phy core which supported multiple protocols including DDR2, FCRAM, RLDRAM and QDR.I have been involved in ASIC/SoC verification (mainly connectivity) using C based re-usable testbenches. I have developed re-usable verification IPs for PCIExpress Gen1, USB20, Ethernet PHY cores to name a few.I had done ASIC to FPGA mapping. My professional goals include :+ functional verification sign-off + research & development of re-usable functional and formal verification methodologies & tools.Specialties: IP Verification Planning, Implementation, Tracking and Delivery.Expertise in PCI Express Bus Protocol.Expertise in System Verilog for verification.Expertise in Verification Methodologies like UVM, OVM and RVM.Expertise in Using C++ in Verification.Expertise in Test automation methods using PERL & Python.Expertise in Agile Project Management Methods.Applied knowledge on Formal Verification Tools & Methods.Applied knowledge on SoC Integration and Verification Methodologies.

Experience

1. Senior Engineer at Ibm

   IBM

   Oct 2024 — Present

Education

• Cochin University of Science and Technology

  Master's degree, Artificial Intelligence

  1994 — 1996

• Indian Institute of Science (IISc)

  Certification in Data Mining, Data Mining & Analytics

  2013 — 2013

Skills

• Functional Verification
• Ic
• Vlsi
• Fpga
• Asic
• Vhdl
• Open Verification Methodology
• Modelsim
• Systemverilog
• C
• Pcie
• Verilog
• Soc