Gopalakrishnan Sadagopan

About Gopalakrishnan Sadagopan

Experienced Physical Design Engineer specializing in RTL-to-GDSII flow for high-speed processor blocks operating at frequencies over 5 GHz. I have worked on Intel\'s 11th, 12th, and 13th generation processors. I have developed expertise in tools such as ICC2, Fusion Compiler, and Prime Time. I am skilled in scripting languages including Shell, Tcl, Python, and Perl, leveraging my abilities to automate tasks and enhance overall efficiency. With 5 years of hands-on experience, I have successfully contributed to improving design quality and reducing time-to-market. Passionate about pushing the boundaries of semiconductor technology.

Experience

1. Senior Physical Design Engineer

   Analog Devices

   Sep 2023 — Present · Bengaluru, IN

   Working on Block Level Physical Implementation.

Education

• TVS Matriculation Higher Secondary School

  Secondary school Leaving Certificate, Maths, Physics, Chemistry, Computer Science

  2007 — 2008

• Thiagarajar College of Engineering

  Bachelor's Degree, Electronics and Communications Engineering

  2010 — 2014

• TVS Matriculation Higher Secondary School

  High School, maths, physics, chemistry, computer science

  2009 — 2010

• National University of Singapore

  Master’s Degree, Nano Electronics

  2015 — 2016

Skills

• Rtl Verification
• Ovm
• Cadence Encounter
• Placement
• Matlab
• Python
• Javascript
• Cadence Virtuoso
• Microsoft Office
• Html
• Rtl Design
• Physical Design
• Synopsys Primetime
• Unix
• Lt Spice
• C#
• .net
• Routing
• Html5
• C
• Floorplanning
• Cadence Spectre
• Perl
• Sql
• Verilog
• Linux
• Very-Large-Scale Integration (Vlsi)
• Static Timing Analysis
• Cascading Style Sheets (Css)
• Java
• Universal Verification Methodology (Uvm)
• Asic Design
• Synopsys Dc Compiler
• C++
• Logic Synthesis
• Cadence Innovus
• Vhdl
• System Verilog
• Angularjs