Gopala Bg

About Gopala Bg

Executive Summary: Synthesis and Scan-insertion Formal Verification at all implementation stages Functional and Test modes Timing Constraints development Lead block level implementation group for 16nm device Pre-layout and Post-layout STA/Timing-closure EDA tools worked on o Cadence RTL Compiler/Genus for Logic synthesis & scan-insertion o Cadence Conformal for Logic Equivalence checking o Cadence Tempus for STATechnical Awareness:• Familiar with scripting languages: Perl Excellent knowledge of ASIC design flow, digital circuit design Worked on Physical Design Implementation at block level using Olympus SOC tool. Knowledge about Conformal ECO flow. Knowledge about Synopsys Design compiler and Primetime tools

Experience

1. Staff Engineer

   Qualcomm

   Dec 2024 — Present

Education

• Sri Venkateswara University

  B.E, Elcectronics and Communication

  2005 — 2009

• Manipal Center for information sciences

  MS, VLSI CAD

  2011 — 2013

Skills

• Compilers
• Logic Synthesis
• Physical Design
• Very-Large-Scale Integration (Vlsi)
• Microcontrollers
• Asic
• C
• Verilog
• Rtl Design
• Integrated Circuit Design
• Static Timing Analysis
• Synopsys Tools
• Systemverilog
• Linux
• Modelsim
• Perl
• Xilinx Ise
• Spice
• Conformal Lec
• Vlsi
• Tcl