Gopal Sridhar
Principal Engineer ASIC Design at Synopsys
- Role
- Principal Engineer at 新思科技股份有限公司
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Gopal Sridhar
Digital Design Engineer with good knowledge of FPGA, ASIC and SoC development processes…
Experience
Principal Engineer
Dec 2024 — Present · Bengaluru, IN
Education
Anna University Chennai
BE, Electrical and Electronics
2001 — 2005
North Carolina State University
MS, Computer Engineering
2005 — 2006
Skills
- Fpga
- Asic
- Hardware Architecture
- Nc-Verilog
- Hardware Design
- Shell Scripting
- Ncsim
- Vlsi
- Integrated Circuit Design
- Modelsim
- Verilog
- Rtl Design
- Field-Programmable Gate Arrays (Fpga)
- C++
- Rtl Coding
- Microcontrollers
- C
- Soc
- Digital Signal Processors
- Xilinx
- Systemverilog
- Perl
- Embedded Systems
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