Gopal Ledange

About Gopal Ledange

Working as a Physical Design Engineer, Having hands-on experience in:* Complete RTL to GDS flow at 5ns,14nm, 28nm,* Synthesis, Static timing analysis, Floor Planning, Power Planning and Placement* Clock tree synthesis, Routing,and Parasitic Extraction.DFT using RC-compiler, ILM flow* Physical verification* Experience in various technologies - 14nm, 28nm* Knowledge on static IR-drop, cross talk and electro-migration analysis, and OCV and AOCV* Expertise in TCL and shell scripts

Experience

1. Physical Design Engineer

   Intel

   Feb 2018 — Present · Bengaluru, IN

Education

• Mahtmaphule College Ahamadpur

  HSC (XII)

  2006 — 2007

• Visvesvaraya National Institute of Technology

  Master’s Degree, VLSI

  2013 — 2015

• Yeshwant Vidyalaya, Ahamadpur Dist-Latur

  SSC (X)

  2004 — 2005

• SVPM COE Malegaon BK

  Bachelor’s Degree, Electronic and Telecommunication

  2008 — 2012

Skills

• Research
• Training
• Xilinx Ise
• Clock Tree Synthesis
• Microsoft Excel
• Powerpoint
• Verilog
• Fpga
• Asic
• Rc Extraction
• Cadence Encounter
• Semiconductors
• Leadership
• Physical Design
• C++
• Vhdl
• Photoshop
• Static Timing Analysis
• Digital Electronics
• Cadence Virtuoso
• Microsoft Office
• Vlsi
• C
• Microsoft Word
• Logic Synthesis
• Matlab
• Rtl Design