Gopal B.
Staff Engineer @ Micron Technology | Technology Development
- Role
- Staff Engineer at Micron Technology
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Gopal B.
11+years of experience in custom layout,memory layout and standard cell layout and physical verification in technologies like 3nm, 4nm, 7nm, 12nm, 14nm, 16nm, 28nm, 40nm. • Expertise in full chip physical verification (DRC, LVS), electrical checks (ERC), timing and noise fixes of critical nets, reliability analysis (sigEM, powerEM, IR.) • Expertise in Cadence Virtuoso (for layout design) and Mentor Graphics Calibre (for physical verification). • Expertise in Virtuoso Layout XL for optimized floorplanning and routing. • Working knowledge on 3D FinFET TSMC16nm, ST 28nm, ST14nm FDSOI technologies. • Knowledge of various layout dependent effects like Antenna violation, EM violation, Latch-up, IR drop, WPE. • Major contribution in very successful projects (Soc chip with 10Ghz processor) at RealSilicon. • Capable of working in a cross functional, multi site team environment spread across various geographies and time zones. • Capable of guiding junior layout designers with project deliverables and schedules.
Experience
Staff Engineer
May 2025 — Present · Hyderabad, IN
Education
UIET Kanpur University
Bachelor of Technology (BTech)
2010 — 2014
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