Gonchigari Vishesh
Staff Engineer, Design Verification
- Role
- Staff Engineer Design Verification at Analog Devices
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Gonchigari Vishesh
5 plus years of experience in Design Verification.Expert in Verilog, System Verilog and UVM.Expert in MIPI CSI2, DPHY, JESD204C/JESD204B, SPI, AHB, APB Protocols.Developed UVM based VIP\'s from scratch.Having good knowledge of verification concepts.NoC IP verification, Verified FuSa and hands on power aware verification,
Experience
Staff Engineer Design Verification
Feb 2026 — Present
Education
Sri Siddhartha Institute of Techology
Bachelor’s Degree, Electronics and Communications Engineering
2010 — 2014
PESIT - South Campus
Master of Technology - MTech, VLSI Design & Embedded Systems
2014 — 2018
Skills
- Keil
- Microsoft Word
- Leadership
- Digital Circuit Design
- System Verilog
- Powerpoint
- Modelsim
- Verilog
- C
- Universal Verification Methodology (Uvm)
- Microsoft Office
- Vhdl
- Xilinx Ise
- Embedded Systems
- Mentor Graphics
- Matlab
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