Aditya Gokhale

About Aditya Gokhale

Experienced R&D professional with over 17 years of rich industry experience in the field of ASIC and FPGA.• Experienced in Design and verification of complex, cutting-edge IP/SoC designs, with focus on RTL/Front-end deliverables.• Active contribution to complete design cycles from concept/specification to tape-out, with strong knowledge and application of digital design concepts.• Experienced in leading a team of 5+ Engineers working on design, constraints, power specs and definition, quality checks of complex IP/SoCs targeting advanced technology nodes (5nm, 7 nm).• Worked with core design team to drive and deliver design implementation for AR/VR SoC achieving low power targets.• Integrated/incorporated several high-speed protocol sub-systems including PCIe RC, LPDDR4 memorycontroller.• Worked with Design Verification team, participating in verification reviews, code and functional coverageclosure, support for gate-level simulation.• Worked actively with DFT/PD/STA teams to deliver constraints, meet required QoR and achieve timingclosure.• Worked with hard-macro teams (PHYs, PLLs, IO PADs, sensors) on SoC integration and test modeimplementation activities.• Experienced in the usage of various industry standard EDA tools and HDLs, standards and specifications.• Working knowledge of ARM bus protocols (APB, AXI, AHB).• University Experience as a Research/Teaching Assistant in VLSI/Digital Design.• Product expertise in the Medical Diagnostics devices/domain.• Skilled writer with extensive experience in technical documentation and a strong passion and talent forblogging.Technical Skills:• Verilog, SystemVerilog, VHDL, UPF, SDC• Magillem, Meridian CDC/RDC, Questa CDC, Spyglass CDC/Lint/LP/DFT, Lintra, VC-LP, Conformal LEC (FEV), Formality, VCS, Verdi, DVE, Fishtail, Duet Caliber• Design Compiler, ECO flow, PrimeTime (analysis), Conformal ECO• Perforce, SVN, GIT, Mantis, Visual Source SafeManagement and Soft Skills:• Excellent communication skills, written and oral, enabling effective inter-departmental interaction as well as customer and field support.• Excellent technical, analytical and logical skills.• Actively involved in providing product/project training to new joinees and trainees, including full operational training as well as imparting technical knowledge.• Excellent individual performer as well as team player.

Experience

1. Technical Lead, Asic Rtl Integration

   Google

   Feb 2024 — Present · Bengaluru, IN

Education

• University of Mumbai

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

• Stony Brook University

  Master of Science - MS, Electrical and Electronics Engineering

• K.J. Somaiya College of Engineering

  Bachelor of Engineering - BE, Electrical and Electronics Engineering

Skills

• Systemverilog
• Isim
• Universal Verification Methodology (Uvm)
• Synplify Pro
• Xilinx Ise
• Xst
• Modelsim
• Vhdl
• Verilog
• Rtl Design
• Rtl Coding
• Field-Programmable Gate Arrays (Fpga)
• Functional Verification
• Fpga
• Verification