Gitesh Sikder
RTL Design Lead at HCLTech | Ex - Researcher at University of Calcutta | Ex - Visiting Researcher at GSI Helmholtz Center for Heavy Ion Research | Ex - Guest Scientist at FAIR
- Role
- Lead Engineer (Rtl Design) at HCLTech
- Location
- Kolkata, WB, IN
- LinkedIn followers
- 500 followers
Experience
Lead Engineer (Rtl Design)
Aug 2021 — Present · Kolkata, IN
RTL Design with Verilog and VHDL2. RTL Code review and debugging3. RTL Detailed Design Documentation4. Creating and analysis of Microarchitecture 5. RTL Debugging6. Proficient in AMBA Protocols 7. Lint Checks (Spyglass VC)
Education
University of Calcutta
Master of Technology - MTech, Computer Engineering and Applications
2015 — 2018
West Bengal University of Technology, Kolkata
Bachelor of Technology - BTech, Information Technology
2009 — 2013
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