Giriraj Kakol

About Giriraj Kakol

Many successful SoC tape-out experience in Intel and TSMC process nodes. • Expert in SoC and Sub-System Physical Verification.(DRC, Density, LVS, Latch-up, Antenna, HV-DRC)• Proficient in Floorplanning, ESD planning and implementation, Bump planning and RDL routing, • Expert in Analog and Digital Hard-IP integration at Sub-System and SoC level. • PD integration and Design automation using TCL scripts, ICV for ICC2 and Fusion Compiler tool env. • Expert in runset coding using Synopsys ICV and Calibre SVRF. • Expert in logistics planning and technical execution of layout clean-up tasks enabling smooth tapeouts. • Deep knowledge of INTEL and TSMC process. Foundry liaison for the team with TSMC/Intel. • Comprehensive knowledge of SoC Physical Design tasks from Netlist/PNR to GDS.• 12 technical publications and poster presentations across internal and external VLSI conferences.

Experience

1. Principal Engineer

   Microsoft

   Sep 2024 — Present

Education

• Visvesvaraya Technological University

  B.E.

  2001 — 2005

• Birla Institute of Technology and Science, Pilani

  MS

  2008 — 2010

Skills

• Lvs
• Cadence
• Shell Scripting
• Vlsi
• Linux
• Modelsim
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Very-Large-Scale Integration (Vlsi)
• Semiconductors
• Layout Versus Schematic (Lvs)
• Soc
• System on a Chip (Soc)
• Static Timing Analysis
• Operating Systems
• Cadence Virtuoso
• Cadence Skill
• Scripting
• Drc
• Perl
• Eda
• Tcl
• Cvs
• Design Rule Checking (Drc)
• Clearcase
• Asic