Praveen Ghanta

Senior Software Architect - Ml Ai @Synopsys Inc

Palo Alto, CA, US
EMAILS
p••••••••@synopsys.com
MOBILE NUMBERS
+14•••••••64

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WORK HISTORY

Sep 2019 — Present

Senior Software Architect - Ml Ai @Synopsys Inc

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Sunnyvale, CA, US

Working on applying Machine Learning/Artificial Intelligence algorithms for Breakthrough Performance and Accuracy improvements in Digital Design Signoff and Implementation Software in advanced Technology nodes. Programming in C/C++, Python, Tcl.

EDUCATION

1996 — 2000

National Institute of Technology Warangal

B.Tech, Electrical Engineering

2000 — 2002

University of Minnesota

MS, Electrical Engineering

2003 — 2007

Arizona State University

PhD, Electrical Engineering

SKILLS

PerlAlgorithmsVerilogTclEdaStatic Timing AnalysisPythonFormal VerificationMatlabUnixLogic SynthesisStatistical ModelingC++PrimetimeVlsiC/C++ ProgrammingStochastic AnalysisGraph AlgorithmsRStatistical Timing AnalysisSoftware DevelopmentProgramming

ABOUT PRAVEEN GHANTA

As a Senior Software Architect - ML/AI at Synopsys, I leverage my PhD in Electrical Engineering and 18+ years of industry experience to develop and apply machine learning and artificial intelligence algorithms for digital design sign-off and implementation software tools. These software tools are essential for designing electronics chips at advanced technology nodes, and are used by the vast majority of chip design companies in the world.I have strong expertise and research interest in the statistical/machine/deep learning of large-scale graphs and circuits, and I have contributed to the industrial advancement of statistical static timing analysis, variation-aware IP library characterization, and yield analysis. I design and develop ML/AI/Graph software and algorithms in C/C++ and Python, and have worked on statistical performance modeling, analysis, and data mining of graphical models with hundreds of millions of nodes. I am passionate about solving challenging problems and creating innovative solutions that enable faster and better chip design.

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