George Koukouras

About George Koukouras

A hands-on contributor ASIC Design/Verification engineer with experience in the ASIC design/verification flow, process, methodology, verification closure, taking a design from concept to sign off. Advanced UVM developer and use on different verification methodologies. Experience in design, SOC architectures (ARM/Tensilica), ASIC flows, Power Domains, Dynamic Clocking, Clock gating, Design Infrastructure, ECO implementation, Architecture-Design closure. Expertise subjects include CPU architectures (ARM), Memory Controllers, CXL, Multi-Layer AXI/AHB (Fabrics), Peripheral Interfaces, Multimedia blocks. Hands-on in Memory bandwidth control, Latency, QoS, Power saving techniques

Experience

1. Verification Architect

   Intel

   Aug 2021 — Present · Raleigh, NC, US

   Verification Architect of Intel\'s PSG Business Unit

Education

• University of Portsmouth

  B.Eng

• University of Sussex

  M.Sc Digital Electronics and Parallel Processing Systems

Skills

• Circuit Design
• Static Timing Analysis
• Digital Electronics
• Synopsys Tools
• Processors
• Project Management
• Ic
• Formal Verification
• System on a Chip (Soc)
• Microarchitecture
• Digital Signal Processors
• Arm
• Rtl Design
• Timing Closure
• Vlsi
• Ncsim
• Nc-Verilog
• Rtl Coding
• Field-Programmable Gate Arrays (Fpga)
• Modelsim
• Systemverilog
• Vmm
• Primetime
• Arm Architecture
• Soc
• Verilog
• Microprocessors
• Emulation
• Simulation
• Amba Ahb
• Application-Specific Integrated Circuits (Asic)
• Fpga
• Asic
• Eda
• Verification Uvm
• Open Verification Methodology
• Functional Verification
• Tcl
• Analog
• Vhdl