Geoffrey H.

About Geoffrey H.

I am a SoC Design Verification Engineer at Intel Corporation, with over 20 years of…

Experience

1. Soc Design Verification Engineer (Transaction Level Simulation and Emulation)

   Intel

   Dec 2020 — Present

   Conduct full-chip design validation activities involving model bringup and end-to-end flow validation within the SoC and package-level models. Updated initial bootstrap code and configuration management software to support new SoC and package features, as well as scale from individual dielet to multi-dielet model configurations. Added new Python code to model stubbed out system component behavior. Mentored junior team members on team workflow, code quality, and debug methods. Owned execution plans for weekly bulk regressions and initial triage of failure buckets. Facilitated training and dojos for department code quality initiatives. Helped coordinate and support other facilitators and track owners.