David Ge

About David Ge

Expert in chip finishing, tapeout and hierartical floor planing, partitioning, chip level and block level P&R and physical verification using Cadence Encounter, Calibre/PVS/HerculeDrives back-end flow methodologyP & R flow QA and router quality checksReliability, power, IR drop, EM checks and fixes.Successfully Taped out many test-chips to TSMC, Global foundry, Samsung and Other foundries.Specialties: Expert in ASIC chip finishing, plance and route, physical verification, reliability verification and flow implementation.Taped-out many various designs such as GDDR PHY, DDR PHY, ARM microprocessor, high-speed disk controller, complex data network and communication controller and high-end graphic engine in 130nm, 90nm, 65nm, 45nm, 28nm,16nm, 14nm, 10nm, 7nm etc.Experience in Low Power design methodology using CPF and Cadence flow.

Experience

1. Physical Layout Verification Engineer

   Rivos Inc

   Nov 2023 — Present · San Jose, CA, US

   Full-chip layout verification, working with subsystem/blocks physical design engineers on closing drc, antenna viotions and lvs mismatches. Responsible for triage drc, antnna violation results to respective physical design block owners for analysis and clean up.

Education

• Oregon State University

  BSEE, Electrical Engineering

  1987 — 1991

• Oregon State University

  MSEE, Electrical Engineering

  1991 — 1993

Skills

• Vlsi
• Application-Specific Integrated Circuits (Asic)
• Physical Verification
• Semiconductors
• Layout Versus Schematic (Lvs)
• Low-Power Design
• Arm
• Verilog
• Eda
• Tcl
• Design Rule Checking (Drc)
• Cadence
• Ic
• Physical Design
• Integrated Circuits (Ic)
• Static Timing Analysis
• Asic
• Mixed Signal
• Very-Large-Scale Integration (Vlsi)
• Debugging
• System on a Chip (Soc)
• Soc