Gaurav Sahasrabudhe

About Gaurav Sahasrabudhe

Make goals, dream big, live with passion”- Tony NewtonBorn and brought up in Mumbai; an incredibly fast city; the city of dreams. The fast paced life kept me on my toes to work hard and efficiently as well as it gave me the courage to dream.Always interested in technological advances seen in Consumer Electronics, I completed my Bachelor of Engineering in Electronics from University of Mumbai. To strengthen my knowledge and become proficient in semiconductors I completed my Masters in Electrical and Computer Engineering at University of Illinois at Chicago. My quest for learning and thirst for knowledge led me to pursue a Post Graduate Diploma in the esteemed institute CDAC (Centre for Development in Advanced Computing)My skills include- EDA Tools : Cadence-Virtuoso, Altera Quartus 13.0, Altera ModelSim- Circuit Simulations: HSPICE, LT-SPICE, Cadence Spectre, MATLAB- Programming Languages: Verilog, VHDL,C, C++- Scripting Languages: Perl, Python Basics- Lab Equipment: Oscilloscopes, Digital Multi meters, Function Generators- Interfaces: Ethernet, UART, RS 232- Operating Systems : Linux, Windows, Mac- Productivity: MS Office (Word, Excel, PowerPoint, Access), Adobe Reader- General: Installation, PC maintenance, PC troubleshooting Areas of interests include-ASIC Design and Verification-Digital Design-VHDL and Verilog Programming-Computer Architecture

Experience

1. Soc Design Engineer

   Intel

   Sep 2020 — Present · Bengaluru, IN

   Responsible for validation of debug IP\'s integrated in Intel\'s Xeon Server processors SOC\'s- Validated entire Debug Trace Fabric (DTF) in Design for Design block of Intel\'s Xeon Server Processor- Created and reviewed the entire verification test plan for this fabric individually- Owned all the Feature validation of the protocol- Assisted in test bench development for entire Design for Debug for the SOC- Executed the verification test plan by developing checkers, input and output monitors, input and output scoreboards- Developed sequences for providing stimulus using UVM methodology. The sequences had self-checks; they also utilized scripts, parsing data from files- Debugged assertions and ran volume validation simulations/regressions. Extensively used VCS for waveform debug- Owner for regression tool as well debug of regression signatures and Integration and re-use continuous improvements towards maintain product quality- Validated debug data in different low power modes include deep sleep, low power states- Validated debug data in different reset modes like warm reset, cold reset and different clock modes like core frequency changes, PLL frequency changes- Use case validation with power aware verification- Developed sequences to hit maximum toggle coverage.

Education

• University of Mumbai

  Bachelor of Engineering (BEng), Electrical and Electronics Engineering

  2008 — 2012

• University of Illinois Chicago

  Master of Science (M.S.), Electrical and Computer Engineering

  2013 — 2015

• Centre for Development of Advanced Computing (C-DAC)

  PG Diploma VLSI, VLSI Design

Skills

• Cadence Spectre
• Perl
• Semiconductors
• Computer Architecture
• Fpga
• Udp
• Asic
• Dhcp
• C++
• Xilinx Ise
• Pcb Design
• Sql
• Powerpoint
• Microcontrollers
• Java
• Tcp/Ip
• Electronics
• System Verilog
• Atpg
• Verilog
• Pspice
• Questasim
• C
• Microsoft Office
• Vlsi
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Cadence Schematic Capture
• Html
• Windows
• Matlab
• Vhdl
• Vlsi Cad
• Cadence Virtuoso
• Digital Circuit Design
• Rtl Design
• Javascript